It would seem that in the not-so-far future the technological leaps in mining should become less frequent. Judging, however, by the news coming from the crazy world of Bitcoin mining, that future is not exactly around the corner.
Yet another ASIC mining company has entered the fray – and this time, with an extremely bold performance claim. Cointerrapromises the smartest chip design and the best price-performance ratio we’ve yet seen in the ASIC market. But can customers afford to wait for it?
The ASIC mining business was all about getting to market first, and we have seen some embarrassing episodes along the way, with some firms repeatedly setting back delivery dates, and revising power-performance ratios.
But designs have also been getting more sophisticated. One of the biggest innovations has been in the process node, which is the size of a typical transistor on a chip. ASIC mining chips have moved from 110 nm, down from 65 nm, to 28 nm designs. The advantage of making transistors smaller is that you can fit more of them on a chip, which means a higher hash rate in the same space, and lower power requirements. KnCMiner garnered lots of attention when it announced a 28 nm design, with units scheduled for release in September.
But it isn’t just about packing more transistors into a smaller space, says Cointerra founder Ravi Iyengar, who says that he is using his chip design experience to optimize the ASIC’s inner circuitry.
“Inside the ASIC chips, there are a number of hash engines and you need to ensure that there is an intelligent distribution of workload,” he says. “You want to ensure that you’re not duplicating them, and that you’re not keeping any of the chips idle. They have to be constantly working, with good and real work.”
Iyengar knows his stuff. He left his job as lead CPU architect at Samsung to found Cointerra. One of his favourite tricks is holding up his Android phone and pointing out that he designed the processor inside it.
Cointerra is designing its ASICs with extra tricks for power efficiency, too, he says. The upshot of it is that he hopes to get to market with the best ASIC units yet in the second half of Q4. It is promising at least 500 Gigahashes per second on a single chip called GoldStrike1 (GS1).
Much of the design innovation is still Iyengar’s secret sauce, and he is building intellectual property around it, he says, but we do know at least one accepted industry technique he’ll be using: increasing the size of each chip (known as the die size).
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